In the calculation, transfer happens every clock because the data pin can reading from different bank. This is similar to the multi-thread latency hiding.
planteurJMTLG
Why is the memory bus "only" 64-bit wide even with modern hardware? Would it be an issue to double the number of pins to allow transfers of 128 bits at a time for instance?
cluo1
Why in the calculation there is a 2 transfers per clock?
kayvonf
@cluo1. See "double data rate" (the DDR in DDR4 memory)
In the calculation, transfer happens every clock because the data pin can reading from different bank. This is similar to the multi-thread latency hiding.
Why is the memory bus "only" 64-bit wide even with modern hardware? Would it be an issue to double the number of pins to allow transfers of 128 bits at a time for instance?
Why in the calculation there is a 2 transfers per clock?
@cluo1. See "double data rate" (the DDR in DDR4 memory)
https://en.wikipedia.org/wiki/Double_data_rate