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I found it useful to consider the overall structure of DRAM organization which is as follows: Channel (consisting of multiple DIMMS) -> DIMM -> rank (which side of the DIMM (front or back)) -> chip (which chip on each side) -> bank -> row -> col


In this case does this meant that we would be able to fetch two cache lines concurrently? Thus, each cache line would have a latency of 8 clocks, just like when we only had 1 channel, but the throughout would be 2x, since we can get two cache lines at once?