Several questions here:
6. Wait for command to be accepted by whom?
7. Who send the data to the bus? the L3 cache or the memory?
blah329
@crabcake I think that number 6 refers to the memory controller within the system. When accessing memory, requests are usually accepted and processed by a memory controller. The way this usually works is that a request can be made, and when the request is complete, the memory controller can send back an acknowledgement to whomever made the request saying that the data is ready to be transferred, at which point the data is received on the bus. Since this is a cache miss and we are reading from memory, that implies that we are probably reading from main memory, since a cache miss would not have occurred had the line been in the L3 cache (by this I mean a total cache miss as in it wasn't in the L1, L2, and L3 caches). Can someone correct me if this is incorrect?
shpeefps
@blah329 I agree. I to think that the command must be accepted by the memory controller, which then fetches the data and sends it through the bus.
Several questions here: 6. Wait for command to be accepted by whom? 7. Who send the data to the bus? the L3 cache or the memory?
@crabcake I think that number 6 refers to the memory controller within the system. When accessing memory, requests are usually accepted and processed by a memory controller. The way this usually works is that a request can be made, and when the request is complete, the memory controller can send back an acknowledgement to whomever made the request saying that the data is ready to be transferred, at which point the data is received on the bus. Since this is a cache miss and we are reading from memory, that implies that we are probably reading from main memory, since a cache miss would not have occurred had the line been in the L3 cache (by this I mean a total cache miss as in it wasn't in the L1, L2, and L3 caches). Can someone correct me if this is incorrect?
@blah329 I agree. I to think that the command must be accepted by the memory controller, which then fetches the data and sends it through the bus.