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To resolve the deadlock in this scenario, P1 must be allowed to flush its dirty line (B) to memory even while waiting for the bus to accept the issuance of BusRdX on line A.


The deadlock will happen in this case if let's say the read request comes (for B) from P0 which is waiting to get the value and P0 also has a modified copy of cache line A. Right?


The deadlock being referred to here is: P1 wants to issue a ReadX for cacheline A, and while it is waiting for the bus to do that, a request for a read of cacheline B appears on the bus. Since P1 has the cacheline in its modified state, it needs to send convey this information and the bus won't be free until it does. But it is waiting for the bus to send its ReadX request. Which can result in a deadlock if P1 doesn't respond to the request on the bus first.


The deadlock in this situation could have been avoided by prioritizing some requests over others. In this case, the BusRdX request would be prioritized over the BusRd request and thus the processor would either service the incoming BusRd request or override the BusRd request with its BusRdX request and then the other processor can resend the BusRed request.