We may have livelock occur if we allow a processor to wrest a cache line away from another processor that was about to write to it.
If this is allowed, then after P1 issues a BusRdX and P2 invalidates its copy of the line, P2 could potentially issue a BusRdX since the bus is now free, and P1 has to drop its copy of the line, possibly before it dirties the cache line. The bus is now free again, so it's possible that P1 will attempt to write and issue another BusRdX, invalidating P2's line, and so on.
A way to prevent this is to ensure that any processor that writes finishes the write before any other processor forces it to invalidate its data.
We may have livelock occur if we allow a processor to wrest a cache line away from another processor that was about to write to it.
If this is allowed, then after P1 issues a BusRdX and P2 invalidates its copy of the line, P2 could potentially issue a BusRdX since the bus is now free, and P1 has to drop its copy of the line, possibly before it dirties the cache line. The bus is now free again, so it's possible that P1 will attempt to write and issue another BusRdX, invalidating P2's line, and so on.
A way to prevent this is to ensure that any processor that writes finishes the write before any other processor forces it to invalidate its data.