Question: Describe an access pattern where a write-back cache generates as much memory traffic as a write-through cache.

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Each time a processor tries to write to a location, it triggers a cache miss.

Suppose we have a 16 byte direct-mapped cache, and one cache line is 8 byte.

int a[8];
for(int i=0;i<100;i+=2){
    a[i%8]=i;
}

It writes to a[0], a[2], a[4], a[6] repeatedly, but such pattern will trigger cache miss because of conflict.

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Another example would be a situation where each line is simply written once.

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So, to sum up the two situations mentioned above, I guess when the writing miss rate is 100%, then a write-back cache generates as much memory traffic as a write-through cache. Whenever we get a write cache hit, the write-back cache just skips one unnecessary access to main memory, thus reducing memory traffic compared to write-through cache.

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