Wouldn't there be a problem if a processor in SC wants to read data, but another processor in SM is writing to the cache line but has not yet updated SC?
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iamk_d___g
@jinghuan: I think the "after some certain time" constraint in last lecture is also needed here.
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kayvonf
@jinghuan: Good question. Imagine P0 has the line in the SC state and P1 has the line in the SM state. Lets say that X is 0. Let's say P1 writes 10 to X in clock t. P0 reads X in clock t and observes 0. P1's update gets to P0 in clock t+1. P0 read X again in clock t+1 and observes 10. Say P1 writes 20 to X in clock t+1. This update gets to P0 in t+2, and P0 observes 20 in t+2.
This system is coherent, since:
All of P1's write occur in program order -- just assume this is the case here --
It obeys write propagation (the write eventually gets to P0)
it obeys write serialization. Both processors agree that the following sequence of writes occurred in the following order.
X = 0, then X = 10, then X = 20
Wouldn't there be a problem if a processor in SC wants to read data, but another processor in SM is writing to the cache line but has not yet updated SC?
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@jinghuan: I think the "after some certain time" constraint in last lecture is also needed here.
This comment was marked helpful 0 times.
@jinghuan: Good question. Imagine P0 has the line in the SC state and P1 has the line in the SM state. Lets say that X is 0. Let's say P1 writes 10 to X in clock t. P0 reads X in clock t and observes 0. P1's update gets to P0 in clock t+1. P0 read X again in clock t+1 and observes 10. Say P1 writes 20 to X in clock t+1. This update gets to P0 in t+2, and P0 observes 20 in t+2.
This system is coherent, since:
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