Question: Can someone describe a sequence of operations that could cause coherence to be violated if the L2 cache did not take special care to invalidate the appropriate line in the L1 upon receiving a BusRdX message over the interconnect?
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jinsikl
Let's say that P0 has X in its L1 and L2 cache, in the shared state. And then P1 broadcasts its desire for exclusive access for a write, by shouting BusRdX on the interconnect. If L2 does not invalidate the L1, then the following can happen. P1 will now think that it has exclusive access, and thus it can modify it without sending any messages on the interconnect. Likewise, since P0 has X in shared state, P0 can read the value of X without sending any messages on the interconnect. This means that any updates made to X by P1 is not visible to P0.
Question: Can someone describe a sequence of operations that could cause coherence to be violated if the L2 cache did not take special care to invalidate the appropriate line in the L1 upon receiving a
BusRdXmessage over the interconnect?This comment was marked helpful 0 times.
Let's say that
P0hasXin its L1 and L2 cache, in the shared state. And thenP1broadcasts its desire for exclusive access for a write, by shoutingBusRdXon the interconnect. If L2 does not invalidate the L1, then the following can happen.P1will now think that it has exclusive access, and thus it can modify it without sending any messages on the interconnect. Likewise, sinceP0hasXin shared state,P0can read the value ofXwithout sending any messages on the interconnect. This means that any updates made toXbyP1is not visible toP0.This comment was marked helpful 0 times.