Above it says that most GPUs do not implement cache coherence. Is there anything in hardware that prevents the problems experienced when operating with cache incoherence, or is that responsibility exclusively up to the programmers?
mangocourage
@lament I don't see how programmers could prevent cache incoherence as hardware caches are controlled by hardware logic. It seems like a way to get coherence at the cost of performance would be turning off private caches.
lament
What I meant wasn't just "can programmers force the caches to be coherent", but rather can programmers write code so that if the caches are incoherent, it does not effect correctness. Programmers can prevent cache incoherence by carefully planning what data each processor touches, assuming that they are able to control what processors do what. As an effect of the size of cache lines, however, I might bring into the cache "old" data that some other process updated but did not commit to memory; this is not a problem as long as we don't use it. In many applications, you probably don't need cache coherence, especially if you can guarantee that every "instruction sequence" that has a unique cache handles unique data.
andymochi
@lament I think it is possible in some situation but we would need more specifics on what kind of memory consistency we have. We went over this later lecture 13, slide 15 and depending on what kind of consistency we have, the programmer might be able to avoid memory pitfalls.
Then again, it's probably still conditional on having 2 or 3 of the 4 memory operation orderings. I imagine some programs are impossible if you only have one memory operation ordering to work with.
Above it says that most GPUs do not implement cache coherence. Is there anything in hardware that prevents the problems experienced when operating with cache incoherence, or is that responsibility exclusively up to the programmers?
@lament I don't see how programmers could prevent cache incoherence as hardware caches are controlled by hardware logic. It seems like a way to get coherence at the cost of performance would be turning off private caches.
What I meant wasn't just "can programmers force the caches to be coherent", but rather can programmers write code so that if the caches are incoherent, it does not effect correctness. Programmers can prevent cache incoherence by carefully planning what data each processor touches, assuming that they are able to control what processors do what. As an effect of the size of cache lines, however, I might bring into the cache "old" data that some other process updated but did not commit to memory; this is not a problem as long as we don't use it. In many applications, you probably don't need cache coherence, especially if you can guarantee that every "instruction sequence" that has a unique cache handles unique data.
@lament I think it is possible in some situation but we would need more specifics on what kind of memory consistency we have. We went over this later lecture 13, slide 15 and depending on what kind of consistency we have, the programmer might be able to avoid memory pitfalls.
Then again, it's probably still conditional on having 2 or 3 of the 4 memory operation orderings. I imagine some programs are impossible if you only have one memory operation ordering to work with.