Can we manually tell the CPU what cache line size to use ? or it is hard-wired when the chip was built ? I am asking because if we could, then a lot of the issues discussed in the class can be resolved, since we just adjust the size depending on our code and the applications we are running.
ericwang
Even we can do so, I think we still need to trade off between cache line number and cache line size.
Besides, CPU need to hold multiple applications at the same time. If these applications have different requirement, how can we choose? It may be not possible to adjust cache line size when the cache is still working.
lament
I am fairly certain that cache size is fixed in hardware, at least in most commercial machines. You can simulate smaller cache sizes by software, but that won't help your performance.
I would be surprised if any machine adjusts the size of any particular cache after manufacturing, but it seems reasonable that some machine changes which cache layers it uses. For example, if a CPU has an l1 and l2 cache, it is conceivable that some CPU has a way of directing traffic in hardware from the l2 cache directly to the CPU as opposed to the l1 cache. All the extra space needed for the extra local buses probably would be an inefficient use of chip area, though. Just speculating.
Can we manually tell the CPU what cache line size to use ? or it is hard-wired when the chip was built ? I am asking because if we could, then a lot of the issues discussed in the class can be resolved, since we just adjust the size depending on our code and the applications we are running.
Even we can do so, I think we still need to trade off between cache line number and cache line size.
Besides, CPU need to hold multiple applications at the same time. If these applications have different requirement, how can we choose? It may be not possible to adjust cache line size when the cache is still working.
I am fairly certain that cache size is fixed in hardware, at least in most commercial machines. You can simulate smaller cache sizes by software, but that won't help your performance.
I would be surprised if any machine adjusts the size of any particular cache after manufacturing, but it seems reasonable that some machine changes which cache layers it uses. For example, if a CPU has an l1 and l2 cache, it is conceivable that some CPU has a way of directing traffic in hardware from the l2 cache directly to the CPU as opposed to the l1 cache. All the extra space needed for the extra local buses probably would be an inefficient use of chip area, though. Just speculating.