Just for clarification: In TSO, the W->R order is only relaxed for individual processors, while in PC the W->R order is relaxed across all processors? Can processors in PC also reorder their own writes and reads as well?
ericwang
Please correct me if I am wrong.
I think these order relaxing terms only make sense when in an individual processor.
If considering operations in multiple processors, the order is not kept at the very beginning. For example, read B in Thread1 and write A in Thread2. Unless we use some synchronize mechanisms.
In this slide, PC relaxes W->R order in individual processors. The different between TSO and PC is whether all processors always get the same value at the same time.
iZac
@mangocourage I think you are correct. I believe processor in PC also can also execute reads before write, but from a perspective of a single thread/ processor, writes are not reordered.
jazzbass
@mangocourage I think that processors are not allowed to reorder writes in TSO or PC. They are only allowed to move reads before of writes, but writes must be done in the same order as declared (else we would be breaking the W ---> W rule).
Additionally (I may be wrong here, please somebody correct me if I'm wrong), I believe TSO and PC behave the same way logically, except that when using PC, processors doesn't need "permission" to read other processors writes early. On the contrary, TSO requires synchronization between processors before reading a write done by other processors.
russt17
Just to clarify, does the first point of TSO also apply to PC on this slide? i.e. for PC can Processor P read B before its write to A is seen by all processors?
apoms
I like to think of these consistency models as saying things about the timelines of read and writes of the processors on a system.
In the TSO model, all processors observe the exact same interleaving of writes to different memory locations on their timeline.
In the PC model, each processor can observe a different interleaving of writes to different memory locations on their timeline.
I say interleaving here because the order of writes by any one processor must be maintained but the way in which that order is merged with the write orders of other processors is dictated by the consistency model.
Just for clarification: In TSO, the W->R order is only relaxed for individual processors, while in PC the W->R order is relaxed across all processors? Can processors in PC also reorder their own writes and reads as well?
Please correct me if I am wrong.
I think these order relaxing terms only make sense when in an individual processor.
If considering operations in multiple processors, the order is not kept at the very beginning. For example, read B in Thread1 and write A in Thread2. Unless we use some synchronize mechanisms.
In this slide, PC relaxes W->R order in individual processors. The different between TSO and PC is whether all processors always get the same value at the same time.
@mangocourage I think you are correct. I believe processor in PC also can also execute reads before write, but from a perspective of a single thread/ processor, writes are not reordered.
@mangocourage I think that processors are not allowed to reorder writes in TSO or PC. They are only allowed to move reads before of writes, but writes must be done in the same order as declared (else we would be breaking the W ---> W rule).
Additionally (I may be wrong here, please somebody correct me if I'm wrong), I believe TSO and PC behave the same way logically, except that when using PC, processors doesn't need "permission" to read other processors writes early. On the contrary, TSO requires synchronization between processors before reading a write done by other processors.
Just to clarify, does the first point of TSO also apply to PC on this slide? i.e. for PC can Processor P read B before its write to A is seen by all processors?
I like to think of these consistency models as saying things about the timelines of read and writes of the processors on a system.
In the TSO model, all processors observe the exact same interleaving of writes to different memory locations on their timeline.
In the PC model, each processor can observe a different interleaving of writes to different memory locations on their timeline.
I say interleaving here because the order of writes by any one processor must be maintained but the way in which that order is merged with the write orders of other processors is dictated by the consistency model.