Is having these 2 memory spaces (1 for host and 1 for a device) the de factor standard for dealing with moving data from CPU to GPU and back, or do other models exists? It seems, intuitively, that one would ideally like 1 large "board" with all processing units on it and a large shared address space (with lots of memory/cache, etc.) Is this what integrated graphics units (i.e. Intel's integrated graphics CPUs) are trying to achieve?
dsaksena
@scedarbaum that's a good question and I'd like to add to it, I believe Having 1 board with all devices connected to it, (i.e. CPU and GPU) will be shared address space model and presently we have a message passing model. Considering the latency of passing messages I guess your proposed model does have an advantage, at the same time tradeoff will be need for locks, but that isn't so bad.
Is having these 2 memory spaces (1 for host and 1 for a device) the de factor standard for dealing with moving data from CPU to GPU and back, or do other models exists? It seems, intuitively, that one would ideally like 1 large "board" with all processing units on it and a large shared address space (with lots of memory/cache, etc.) Is this what integrated graphics units (i.e. Intel's integrated graphics CPUs) are trying to achieve?
@scedarbaum that's a good question and I'd like to add to it, I believe Having 1 board with all devices connected to it, (i.e. CPU and GPU) will be shared address space model and presently we have a message passing model. Considering the latency of passing messages I guess your proposed model does have an advantage, at the same time tradeoff will be need for locks, but that isn't so bad.