From http://www.ccs.neu.edu/course/com3200/parent/NOTES/DDR.html:
"The auto-precharge option for READ and WRITE allows for a fast, automatic PRECHARGE command after READ/WRITE. However, PRECHARGE will close the current page. So, auto-precharge should only be used if it is known that the next access to this memory bank will be to a different memory page. This is a prediction about the future. Most chipsets prefer to assume spatial locality, and so not use auto-precharge."
While this is technically written about a full memory bank and not a single row, it seems reasonable to assume that DRAM uses the same logic for individual rows. So, it looks like precharging should only be used when we know that the next byte access is actually located in a different row.
msebek
In the news recently was the "Row Hammer" attack on DRAM, where Onur Mutlu (CMU ECE Computer Architecture prof) et al. showed that repeated reading (1000x times) of a single row would cause nearby rows to leak charge faster, allowing an attacker to modify data that they would otherwise be unable to (and get sudo and stuff). Afaik, it's one of the only known attacks that leverage software to exploit an analog abstraction.
Published in IEEE, hung out on Hacker News for a number of days, hit all the major tech news sites.
The intro to DRAM provided by 418 is enough to understand the attached paper.
Just a point of curiosity: How badly can precharge and activation steps bite us? What's a ballpark figure for how long they take relative to column access?
funkysenior15
I'm not sure I completely understand PRE, CAS and RAS. I think I'm conflating these ideas with each other. For the benefit of me (and others reading), can someone elaborate?
subliminal
According to me, PRE involves getting the bit lines to the row buffer ready for transfer, RAS involves getting the relevant row in the DRAM chip ready for transfer,and into the row buffer, and CAS involves picking and transferring the pertinent (bus-width) amount of bytes onto the bus.
aznshodan
@funkysenior15
PRE: in PRE all its doing is writing the bits in the row buffer back to the original row. For example, if the row buffer has the bits from row 5, then at precharge, it reads the bits at the row buffer and writes them back to row 5. The reason why we do this is because the bits in the row buffer can be different from the bits in row 5 even though they represent the same row.
RAS: for activation, all it's doing is reading the row and writing it to the Row Buffer
CAS: column activation is outputting the bits(the "red" portion of the Row Buffer) from the Row Buffer using a multiplexer. Multiplexer simply selects the bits that were requested by the Memory Controller and outputs them to the data bus.
From http://www.ccs.neu.edu/course/com3200/parent/NOTES/DDR.html:
"The auto-precharge option for READ and WRITE allows for a fast, automatic PRECHARGE command after READ/WRITE. However, PRECHARGE will close the current page. So, auto-precharge should only be used if it is known that the next access to this memory bank will be to a different memory page. This is a prediction about the future. Most chipsets prefer to assume spatial locality, and so not use auto-precharge."
While this is technically written about a full memory bank and not a single row, it seems reasonable to assume that DRAM uses the same logic for individual rows. So, it looks like precharging should only be used when we know that the next byte access is actually located in a different row.
In the news recently was the "Row Hammer" attack on DRAM, where Onur Mutlu (CMU ECE Computer Architecture prof) et al. showed that repeated reading (1000x times) of a single row would cause nearby rows to leak charge faster, allowing an attacker to modify data that they would otherwise be unable to (and get sudo and stuff). Afaik, it's one of the only known attacks that leverage software to exploit an analog abstraction.
Published in IEEE, hung out on Hacker News for a number of days, hit all the major tech news sites.
The intro to DRAM provided by 418 is enough to understand the attached paper.
Paper: http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf
Just a point of curiosity: How badly can precharge and activation steps bite us? What's a ballpark figure for how long they take relative to column access?
I'm not sure I completely understand PRE, CAS and RAS. I think I'm conflating these ideas with each other. For the benefit of me (and others reading), can someone elaborate?
According to me, PRE involves getting the bit lines to the row buffer ready for transfer, RAS involves getting the relevant row in the DRAM chip ready for transfer,and into the row buffer, and CAS involves picking and transferring the pertinent (bus-width) amount of bytes onto the bus.
@funkysenior15 PRE: in PRE all its doing is writing the bits in the row buffer back to the original row. For example, if the row buffer has the bits from row 5, then at precharge, it reads the bits at the row buffer and writes them back to row 5. The reason why we do this is because the bits in the row buffer can be different from the bits in row 5 even though they represent the same row.
RAS: for activation, all it's doing is reading the row and writing it to the Row Buffer
CAS: column activation is outputting the bits(the "red" portion of the Row Buffer) from the Row Buffer using a multiplexer. Multiplexer simply selects the bits that were requested by the Memory Controller and outputs them to the data bus.