I'm curious about the controller for the embedded DRAMs (eDRAMs) on chips. Do they have a similar controller like a cache would have on the chip, or do they have a specialized dedicated memory controller separately from the cache?
solovoy
This actually reminds me of this slide. If people decide to add another level of "cache" (though called eDRAM), does this mean the data traffic has been changing due to new computation tasks/paradigm?
sanchuah
I am curious about whether the memory protocol(like bus ...) eDRAM is similar to what we discussed in "Basic Snooping-Based Multi-Processor Implementation".
yuel1
Does eDRAM require additions to the ISA to explicitly access data from the eDRAM, or does it serve as an L4 cache effectively.
I'm curious about the controller for the embedded DRAMs (eDRAMs) on chips. Do they have a similar controller like a cache would have on the chip, or do they have a specialized dedicated memory controller separately from the cache?
This actually reminds me of this slide. If people decide to add another level of "cache" (though called eDRAM), does this mean the data traffic has been changing due to new computation tasks/paradigm?
I am curious about whether the memory protocol(like bus ...) eDRAM is similar to what we discussed in "Basic Snooping-Based Multi-Processor Implementation".
Does eDRAM require additions to the ISA to explicitly access data from the eDRAM, or does it serve as an L4 cache effectively.