What are some examples of communication misses? From what I remember in class, we briefly talked about a processor trying to access memory that is cached in a different processor. Does this count as a communication miss, or a cold miss (which could have been prevented by perhaps a different assignment of tasks by the programmer)?

Here's a simple explanation for now, and we'll get back to this big time when we discuss the concept of cache coherence:

Consider a basic multi-core processor with 2 cores and an L1 cache per core. Imagine Thread 0 on core 0 writes the value 1 to address X. Because of the access, the data is not sitting in the L1 cache of core 0. Now say thread 1 on core 1 tries to read from address X. Although the value is cached on core 0, it is not cached on core 1 and so the read will trigger a cache miss on core 1. This is an example of a communication miss. Core 1 took a miss because the data is needed was not in its cache (the data was in cache, just the wrong one.)

The situation is even more apparent when both threads are trying to write to address X. As we'll discuss in a couple of lectures, the cache line containing X is going to bounce back and forth between core 0 and core 1, causing many misses that would not exist in the sequential version of the program.

So one address can only be in one cache at a time? Is there any way to synchronize this so that whenever a value is updated, both caches get the new value?

@HLAHat. And I'll spent three lectures on this precise topic soon. But notice that your question "Is there any way to synchronize this so that whenever a value is updated, both caches get the new value?" gets at the essence of the point. That communication is necessary!

A good illustration of one potential challenge is here on slide 32.

I think communication loss is due to false sharing.